Job Title:

Design Verification Engineer

Company:

Ridge IT

Location:

Toronto, ON

Closing Date:

February 28, 2020


Design Verification Engineer (UVM/OVM)

  • Development of verification plans at full-chip (SoC) and block levels for complex designs
  • Ability to describe test scenarios and coverage metrics for functional verification
  • Hands-on experience with large, automated, metric-driven simulation environments
  • Hands-on experience with debug tools, bug tracking and quality metrics and closure
  • Synopsys (VCS) and/or Cadence simulation/verification tools
  • 8-15 years’ industry experience, BS EE or CE, MS preferred

Roles & Responsibilities

  • Building teams and guiding towards research, design, develop, and test electronics circuits, components and chips in CPU, telecommunication, networking, storage and graphic industry.
  • Derive the requirements from the specifications and architect UVM/OVM/VMM verification environment using latest verification platform and tools based on HVL and System Verilog or VHDL.
  • You will be responsible for developing and reviewing verification plans, strategy, guide development and integration of re-usable test environments, system level scenarios, performance measurement and stress testing, assertions, power aware simulations, GLS, x-prop and test vectors.
  • Familiarity/experience with formal verification and/or assertions is a plus.
  • Develop a detailed schedule and task list for the team and track it in terms of time and quality to guide it to successful closure.

TO APPLY:

If you have the skills and experience required for this position, please forward your resume to:

E-mail: hr@ridgeitsolutionsinc.com



Posted 2020-02-10








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